1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for determining contact opening dimensions using scatterometry.
2. Description of the Related Art
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconductive substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections. Many modem integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections must be made in multiple layers to conserve plot space on the semiconductive substrate.
The conductive interconnections are typically accomplished through the formation of a plurality of conductive lines and conductive plugs, commonly referred to as contacts or vias, formed in alternative layers of dielectric materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another.
A contact is generally used to define an interconnection (e.g., using polysilicon or metal) to an underlying polysilicon layer (e.g., source/drain or gate region of a transistor), while a via denotes a metal to metal interconnection. In either case, a contact opening is formed in an insulating layer overlaying the conductive member. A second conductive layer is then formed over the contact opening and electrical communication is established with the conductive member.
Typically contact openings are formed by etching the underlying insulating layer through a patterned layer of photoresist material using an anisotropic etch process. Control of the photoresist patterning and etching processes is important for ensuring the integrity and proper dimensions of the contact opening. If the contact opening dimensions (e.g., size, depth, sidewall profile) are outside of design tolerances, the electrical properties of the subsequently formed contact or via may be compromised.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a test structure including a plurality of lines and a plurality of contact openings defined in the lines.
Another aspect of the present invention is seen in a method for determining contact opening dimensions. The method includes providing a wafer having a test structure comprising a plurality of lines and a plurality of contact openings defined in the lines; illuminating at least a portion of the contact openings with a light source; measuring light reflected from the illuminated portion of the contact openings to generate a reflection profile; and determining a dimension of the contact openings based on the reflection profile.
Yet another aspect of the invention is seen in a metrology tool. The metrology tool is adapted to receive a wafer having a test structure comprising a plurality of lines and a plurality of contact openings defined in the lines. The metrology tool includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the contact openings. The detector is adapted to measure light reflected from the illuminated portion of the contact openings to generate a reflection profile. The data processing unit is adapted to determine a dimension of the contact openings based on the reflection profile.